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KMM366S403CTL
Revision History Revision .3 (Mar. 1998)
PC66 SDRAM MODULE
*Some Parameter values & Characteristics of comp. level are changed as below : - Input leakage currents (Inputs) : 5uA to 1uA. - Input leakage currents (I/O) : 5uA to 1.5uA. - Cin to be measured at VDD = 3.3V, TA = 23C, f = 1MHz, VREF = 1.4V 200mV. - AC Operating Condition is changed as defined : VIH(max) = 5.6V AC. The overshoot voltage duration is 3ns. VIL(min) = -2.0V AC. The undershoot voltage duration is 3ns.
REV. 3 Mar. '98
KMM366S403CTL
KMM366S403CTL SDRAM DIMM
PC66 SDRAM MODULE
4Mx64 SDRAM DIMM based on 2Mx8, 4K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION
The Samsung KMM366S403CTL is a 4M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung KMM366S403CTL consists of sixteen CMOS 2M x 8 bit Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate. Two 0.33uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The KMM366S403CTL is a Dual In-line Memory Module and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
FEATURE
* Performance range Part No. KMM366S403CTL-G0 * * * * * Max Freq. (Speed) 100MHz (10ns @ CL=3)
Burst mode operation Auto & self refresh capability (4096 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock * Serial presence detect with EEPROM * PCB : Height (1,100mil) , double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 *CB0 *CB1 VSS NC NC VDD WE DQM0 Front Pin Front Pin DQ18 DQ19 VDD DQ20 NC *VREF CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC NC **SDA **SCL VDD 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 *CB4 *CB5 VSS NC NC VDD CAS DQM4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 *A11 VDD CLK1 *A12 VSS CKE0 CS3 DQM6 DQM7 *A13 VDD NC NC *CB6 *CB7 VSS DQ48 DQ49 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back DQ50 DQ51 VDD DQ52 NC *VREF NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC **SA0 **SA1 **SA2 VDD 29 DQM1 57 58 CS0 30 59 31 DU 60 32 VSS 61 33 A0 62 34 A2 63 35 A4 64 36 A6 65 37 A8 38 A10/AP 66 67 39 *BA1 68 40 VDD 69 41 VDD 42 CLK0 70 71 43 VSS 72 44 DU 73 45 CS2 46 DQM2 74 47 DQM3 75 76 48 DU 77 49 VDD 78 50 NC 79 51 NC 52 *CB2 80 53 *CB3 81 82 54 VSS 55 DQ16 83 56 DQ17 84
PIN NAMES
Pin Name A0 ~ A10/AP BA0 DQ0 ~ DQ63 CLK0 ~ CLK3 CS0 ~ CS3 RAS CAS WE DQM0 ~ 7 VDD VSS *VREF SDA SCL SA0 ~ 2 DU NC Function Address input (Multiplexed) Select bank Data input/output Clock input Chip select input Row address strobe Column address strobe Write enable DQM Power supply (3.3V) Ground Power supply for reference Serial data I/O Serial clock Address in EEPROM Dont use No connection
CKE0 ~ CKE1 Clock enable input
* These pins are not used in this module. ** These pins should be NC in the system which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
REV. 3 Mar. '98
KMM366S403CTL
PIN CONFIGURATION DESCRIPTION
Pin CLK CS Name System clock Chip select
PC66 SDRAM MODULE
Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA10, Column address : CA0 ~ CA8 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic.
CKE
Clock enable
A0 ~ A10/AP Address BA0 RAS CAS WE DQM0 ~ 7 DQ0 ~ 63 VDD/VSS Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground
REV. 3 Mar. '98
KMM366S403CTL
FUNCTIONAL BLOCK DIAGRAM
CS1 CS0 DQM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS3 CS2 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 A0 ~ An, BA0 RAS CAS WE CKE0 10 DQn VDD Vss * * * * Two 0.33uF Capacitors per each SDRAM To all SDRAMs Every DQpin of SDRAM * DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 * DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 * CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 * DQM4 CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM5 CS CS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 *
PC66 SDRAM MODULE
U0
U8
DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 *
CS
U4
DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
U12
U1
U9
DQM CS DQ0 DQ1 DQ2 U5 DQ3 DQ4 DQ5 DQ6 DQ7
DQM CS DQ0 DQ1 DQ2 U13 DQ3 DQ4 DQ5 DQ6 DQ7
* DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 * DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
* CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
* DQM6 CS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7 * DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 * DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Serial PD VDD SCL 10K CKE1 * SDRAM U8 ~ U15 * * 10 A0 A1 A2 SDA CS CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS
U2
U10
U6
U14
CS
CS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
U3
U11
U7
U15
SDRAM U0 ~ U15 SDRAM U0 ~ U15 SDRAM U0 ~ U15 SDRAM U0 ~ U15 SDRAM U0 ~ U7
SA0 SA1 SA2 10 U0/U1/U2/U3 U4/U5/U6/U7 U8/U9/U10/U11 U12/U13/U14/U15
*
CLK0/1/2/3
REV. 3 Mar. '98
KMM366S403CTL
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS
PC66 SDRAM MODULE
Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 16 50 Unit V V C W mA
Notes : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) Parameter Supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current (Inputs) Input leakage current (I/O pins) Symbol VDD VIH VIL VOH VOL IIL IIL Min 3.0 2.0 -0.3 2.4 -16 -3 Typ 3.3 3.0 0 Max 3.6 VDDQ+0.3 0.8 0.4 16 3 Unit V V V V V uA uA 1 2 IOH = -2mA IOL = 2mA 3 3,4 Note
Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. Dout is disabled, 0V VOUT VDDQ.
CAPACITANCE
(VDD = 3.3V, TA = 23C, f = 1MHz, VREF = 1.4V 200 mV) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 COUT Min 60 60 35 25 25 15 10 Max 90 90 55 35 35 25 20 Unit pF pF pF pF pF pF pF
Parameter Input capacitance (A0 ~ A10/AP, BA0) Input capacitance (RAS, CAS, WE) Input capacitance (CKE0 ~ CKE1) Input capacitance (CLK0 ~ CLK3) Input capacitance (CS0 ~ CS3) Input capacitance (DQM0 ~ DQM7) Data input/output capacitance (DQ0 ~ DQ63)
MAXIMUM TRACE LENGTHS
Signal A0 ~ A10/AP BA0 RAS CAS WE Max lengths 8.0 8.0 8.0 8.0 8.0 Unit Inches Inches Inches Inches Inches Signal CKE0 ~ CKE1 CS0 ~ CS3 DQM0 ~ DQM7 DQ0 ~ DQ63 Max lengths 5.5 4.0 3.0 2.0 Unit Inches Inches Inches Inches
REV. 3 Mar. '98
KMM366S403CTL
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Symbol Test Condition Burst length = 1 tRC tRC(min) IOL = 0 mA CKE VIL(max), tCC = 15ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 15ns Input signals are changed one time during 30ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 15ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 15ns Input signals are changed one time during 30ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IOL = 0 mA Page burst 2Banks activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V 3 2 CAS Latency
PC66 SDRAM MODULE
Version -0 800 16 16 240
Unit
Note
Operating current (One bank active) Precharge standby current in power-down mode
ICC1 ICC2P ICC2PS ICC2N
mA
1
mA
Precharge standby current in non power-down mode ICC2NS Active standby current in power-down mode ICC3P ICC3PS ICC3N ICC3NS
mA 64 32 16 400 240 960 mA 880 800 16 mA mA 2 1 mA mA
mA
Active standby current in non power-down mode (One bank active)
Operating current (Burst mode) Refresh current Self refresh current
ICC4
ICC5 ICC6
Notes : 1. Measured with outputs open. 2. Refresh period is 64ms.
REV. 3 Mar. '98
KMM366S403CTL
AC OPERATING TEST CONDITIONS
Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition
3.3V
PC66 SDRAM MODULE
(VDD = 3.3V 0.3V, TA = 0 to 70C) Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2
Vtt = 1.4V
Unit V V ns V
1200 Output 870 * * * 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50 *
50
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 Version -0 20 26 26 50 100 80 12 1 1 1 2 1 ns ns ns ns us ns ns CLK CLK CLK ea 1 2 2 2 3 4 1 1 1 1 Unit Note
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop.
REV. 3 Mar. '98
KMM366S403CTL
PC66 SDRAM MODULE
AC CHARACTERISTICS (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
Parameter CAS latency=3 CAS latency=2 CLK to valid output delay Output data hold time CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 tCH tCL tSS tSH tSLZ tSHZ tOH 3 3 3.5 3.5 2.5 1 1 7 8 ns ns ns ns ns ns 3 3 3 3 2 tSAC Symbol Min CLK cycle time tCC 10 13 7 8 ns 2 ns 1,2 -0 Max 1000 ns 1 Unit Note
CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3 CAS latency=2
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
REV. 3 Mar. '98
KMM366S403CTL
FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE
KMM366S403CTL-G0
Frequency 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) 60MHz (16.7ns) CAS Latency 3 3 2 2 2 tRC 80ns 8 7 7 6 5 tRAS 50ns 5 5 4 4 3 tRP 26ns 3 3 2 2 2 tRRD 20ns 2 2 2 2 2
PC66 SDRAM MODULE
(Unit : Number of clock) tRCD 26ns 3 3 2 2 2 tCCD 10ns 1 1 1 1 1 tCDL 10ns 1 1 1 1 1 tRDL 12ns 2 1 1 1 1
REV. 3 Mar. '98
KMM366S403CTL
SIMPLIFIED TRUTH TABLE
Command Register Mode register set Auto refresh Refresh Entry Self refresh Exit L H H
CKEn-1 CKEn CS RAS CAS
PC66 SDRAM MODULE
WE DQM BA0 A10/AP A9 ~ A0 Note
H H
X H L H X X
L L L H
L L H X L H
L L H X H L
L H H X H H
X X
OP code X
1,2 3 3
X X X V V
X Row address L H
Column address (A0 ~ A8) Column address (A0 ~ A8)
3 3
Bank active & row addr. Read & column address Write & column address Burst stop Precharge Bank selection Both banks Clock suspend or active power down Entry Exit Entry Precharge power down mode Exit DQM No operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable
L L
4 4,5 4 4,5 6
H H H
X X X
L L L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
X X X
V
L H X
V X
L H
X
H L H
L H L
X X X X X X V X X 7
X H L
L H H
H
H L
X
H L
X H
X H
X H
X
(V=Valid, X=Dont care, H=Logic high, L=Logic low) Notes :1. OP Code : Operand code A0 ~ A10/AP, BA0 : Program keys. (@ MRS) 2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at both banks precharge state. 4. BA0 : Bank select address. If "Low" at read, write, row active and precharge, bank A is selected. If "High" at read, write, row active and precharge, bank B is selected. If A10/AP is "High" at row precharge, BA0 is ignored and both banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
REV. 3 Mar. '98
KMM366S403CTL
PACKAGE DIMENSIONS
PC66 SDRAM MODULE
Units : Inches (Millimeters)
5.250 (133.350) 0.118 (3.000) 5.014 (127.350)
0.054 (1.372)
R 0.079 (R 2.000) 0.157 0.004 (4.000 0.100)
1.100 (27.94)
0.118 (3.000)
.118DIA 0.004 (3.000DIA 0.100) 0.350 (8.890)
A 0.250 (6.350) .450 (11.430) 1.450 (36.830)
B 0.250 (6.350)
C
2.150 (54.61) 4.550 (115.57)
0.100 Min (2.540 Min)
0.700 (17.780)
0.150 Max (3.81 Max) (5.08 Min) 0.200 Min
0.050 0.0039 (1.270 0.10)
0.250 (6.350)
0.250 (6.350)
(2.540 Min)
0.100 Min
0.039 0.002 (1.000 0.050)
0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100)
0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100)
0.010 Max (0.250 Max) 0.050 (1.270)
Detail A
Detail B
Detail C
Tolerances : 0.005(.13) unless otherwise specified The used device is 2Mx8 SDRAM, TSOP SDRAM Part No. : KM48S2020CT
REV. 3 Mar. '98

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